1. Field of the Invention
The present invention pertains to a clock supply device and a clock supply method for supplying clocks to a predetermined circuit device, and more particularly, to a clock supply device and a clock supply method by which high-precision clocks are supplied to a predetermined circuit device with the use of a holdover function that is attached to the PLL circuit of the clock supply device, even if an error occurs in the input frequency in a device that manages frequencies.
2. Description of the Related Art
There has been a clock supply device that is designed to generate a clock in phase synchronization with the frequency of an input reference signal serving as a reference, and also generate a different clock with a frequency that is generated in the past, instead of the above clock, in a case where an error occurs in the input reference signal. Such a clock supply device has a holdover function attached to a PLL (Phase Locked Loop) circuit. The holdover function is designed to output a clock having the same frequency as the clock that is output immediately before an error.
In such a clock supply device, it is necessary to maintain the same frequency with high precision over a long period of time after an error occurs in the input reference signal. To achieve this effect, a technique has been suggested to select a clock signal determined to have the highest quality among clock signals obtained as results of dividing operations by divider circuits in the PLL circuit, and to use the selected clock signal at the time of holdover (see Japanese Patent Application Laid-Open No. 2002-232407 (paragraph [0006], FIG. 1), for example).
By the suggested technique, the divider circuits divide extracted clocks into phase comparison frequencies, so as to obtain divided input clocks. A select signal generating circuit selects the divided input clock determined to have the highest quality, based on detection quality information and input break information. Therefore, the circuit size to accommodate those operations becomes larger. Also, even if the clock signal determined to have the highest quality is selected, the quality of the function to maintain the frequency of the selected clock signal is questionable. To counter those problems, the use of a voltage-controlled oscillator with high stability has been suggested to increase the reliability of the PLL circuit at the time of holdover.
FIG. 9 shows a conventional clock supply device that has a high stability voltage-controlled oscillator provided in a PLL circuit. The clock supply device 100 has a holdover circuit unit 102 attached to a PLL circuit 101.
Here, the PLL circuit 101 includes: a phase comparator 113 that compares the phase of an input reference signal 103 with the phase of an output 112 of a divider 111; a memory 115 that has the phase comparison result 114 written therein; a selector 117 that receives the phase comparison result 114 and an output 116 of the memory 115, and selects either the result 114 or the output 116; a digital-analog converter 119 that receives an output 118 of the selector 117, and converts the output 118 into an analog signal; and a high-stability voltage-controlled oscillator 122 that receives an output 120 of the digital-analog converter 119, and outputs an output clock signal 121 having a frequency according to the output 120. The output clock signal 121 output from the high-stability voltage-controlled oscillator 122 serves as an output signal of the PLL circuit 101, and also branches into the divider 111. In the PLL circuit 101 having such a structure, the high-stability voltage-controlled oscillator 122 oscillates at a frequency corresponding to a voltage according to the phase difference between the input reference signal 103 having the predetermined frequency and the output 112 of the divider 111. Accordingly, the output clock signal 121 having the frequency according to the dividing rate of the divider 111 is output.
The memory 115 and the selector 117 provided on the output side of the memory 115 forms a part of the holdover circuit unit 102, and receive a monitor result 132 from a frequency error monitoring circuit 131. Here, the frequency error monitoring circuit 131 receives both the input reference signal 103 and a clock signal 134 output from a high-stability fixed oscillator 133, and monitors occurrences of frequency errors such as breaking of the input reference signal 103. The memory 115 stores the phase comparison result 114 from the phase comparator 113 as a digital value. When the frequency error monitoring circuit 131 detects an error in the input reference signal 103, the selector 117 selects a digital value stored before the error detection, so as to realize a holdover state.
In a case where an error is not detected in the frequency of the input reference signal 103, the selector 117 selects and sets the phase comparison result 114 as the output 118. In a case where an error is detected in the frequency of the input reference signal 103, the selector 117 selects the output 116 of the memory 115, instead. The digital-analog converter 119 then converts the selected value into analog data. The high-stability voltage-controlled oscillator 122 then generates the output clock signal 121 with high stability, based on the frequency corresponding to the analog data as a fixed value. In this manner, the substitute frequency can be maintained when an error occurs.
An example of a conventional clock supply device has been described above. The voltage-controlled oscillator formed with the phase comparator 113, the digital-analog converter 119, the divider 111 and the high-stability voltage-controlled oscillator 122, which are the fundamental components of the PLL circuit 101, is well known to those skilled in the art. Therefore, explanation of the operation to be performed by the voltage-controlled oscillator is omitted here.
The above clock supply device as a PLL circuit equipped with a conventional holdover function has the problem of requiring a high-stability fixed oscillator for detecting with high precision the frequency output from the PLL circuit immediately before a frequency error occurs. To maintain the frequency observed immediately before the error and achieve the holdover characteristics satisfying certain standards after the error occurrence, it is necessary to use the high-stability voltage-controlled oscillator 112 that receives a high-precision frequency detected as the frequency output immediately before the error, and can oscillate in a stable manner even when an environmental change such as a temperature change occurs within an allowable error range. In this manner, the high-stability voltage-controlled oscillator 122, instead of a voltage-controlled oscillator normally used in a PLL circuit, is necessary.
As described above, the conventional clock supply device equipped with the holdover function requires two high stability oscillators in one circuit. Those high stability oscillators involve other additional components such as circuit components for maintaining the same temperature so as to stabilize oscillations. As a result, the device size becomes physically large, and the production costs and the product prices also become high.